The Bus Interface Unit (BIU), and The Execution Unit (EU).

 

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It performs various machine cycles such as memory read, I/O read, etc. to transfer data between memory and I/O devices. 

BIU performs the following functions are as follows: 

• It generates the 20-bit physical address for memory access.
• It fetches instructions from the memory.
• It transfers data to and from the memory and I/O.
• Maintains the 6-byte pre-fetch instruction queue(supports pipelining).

BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and an Address Generation Circuit. 

Instruction Pointer (IP): 

• It is a 16-bit register. It holds offset of the next instructions in the Code Segment.
• IP is incremented after every instruction byte is fetched.
• IP gets a new value whenever a branch instruction occurs.  
• CS is multiplied by 10H to give the 20-bit physical address of the Code Segment.
• The address of the next instruction is calculated by using the formula CS x 10H + IP.

Example: 

CS = 4321H IP = 1000H 
then CS x 10H = 43210H + offset =  44210H  
Here Offset = Instruction Pointer(IP)

This is the address of the next instruction. 

Code Segment register: (16 Bit register): CS holds the base address for the Code Segment. All programs are stored in the Code Segment and accessed via the IP. 

Data Segment register: (16 Bit register): DS holds the base address for the Data Segment. 

Stack Segment register: (16 Bit register): SS holds the base address for the Stack Segment. 

Extra Segment register: (16 Bit register): ES holds the base address for the Extra Segment. 

Please note that segments are present in memory and segment registers are present in Microprocessor.
Segment registers store starting address of each segments in memory.
 

Address Generation Circuit: 

• The BIU has a Physical Address Generation Circuit.
• It generates the 20-bit physical address using Segment and Offset addresses using the formula: 
• In Bus Interface Unit (BIU) the circuit shown by the Σ symbol is responsible for the calculation unit which is used to calculate the physical address of an instruction in memory.

Physical Address = Segment Address x 10H + Offset Address

6 Byte Pre-fetch Queue: 

• It is a 6-byte queue (FIFO).
• Fetching the next instruction (by BIU from CS) while executing the current instruction is called pipelining.
• Gets flushed whenever a branch instruction occurs. 
• The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that can have in 8086 is 6 bytes. Hence to cover up all operands and data fields of maximum size instruction in 8086 Microprocessor there is a Pre-Fetch queue is 6 Bytes.
• The pre-Fetch queue is connected with the control unit which is responsible for decoding op-code and operands and telling the execution unit what to do with the help of timing and control signals.
• The pre-Fetch queue is responsible for pipelining and because of that 8086 microprocessor is called fetch, decode, execute type microprocessor. Since there are always instructions present for decoding and execution in this queue the speed of execution in the microprocessor is gradually increased.
• When there is a 2-byte space in the instruction pre-fetch queue then only the next instruction will be pushed into the queue otherwise if only a 1-byte space is vacant then there will not be any allocation in the queue. It will wait for a spacing of 2 bytes in subsequent queue decoding operations.
• Instruction pre-fetch queue works in a sequential manner so if there is any branch condition then in that situation pre-fetch queue fails. Hence to avoid chaos instruction queue is flushed out when any branch or conditional jumps occur.

2.prefetch unit:

The Prefetch Unit in the 8086 microprocessor is a component responsible for fetching instructions from memory and storing them in a queue. The prefetch unit allows the 8086 to perform multiple instruction fetches in parallel, improving the overall performance of the microprocessor.

The prefetch unit consists of a buffer and a program counter that are used to fetch instructions from memory. The buffer stores the instructions that have been fetched and the program counter keeps track of the memory location of the next instruction to be fetched. The prefetch unit fetches several instructions ahead of the current instruction, allowing the 8086 to execute instructions from the buffer rather than from memory.

This parallel processing of instruction fetches helps to reduce the wait time for memory access, as the 8086 can continue to execute instructions from the buffer while it waits for memory access to complete. This results in improved overall performance, as the 8086 is able to execute more instructions in a given amount of time.

The prefetch unit is an important component of the 8086 microprocessor, as it allows the microprocessor to work more efficiently and perform more instructions in a given amount of time. This improved performance helps to ensure that the 8086 remains competitive in its performance and capabilities, even as technology continues to advance.

3. The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers, the Instruction Register and Instruction Decoder, and the Flag/Status Register. 

1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic operations using the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.(Control Unit)
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.

8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store intermediate values during execution. Each of these has two 8-bit parts (higher and lower). 

• AX register: (Combination of AL and AH Registers)
  It holds operands and results during multiplication and division operations. Also an accumulator during String operations. 
   
• BX register: (Combination of BL and BH Registers)
  It holds the memory address (offset address) in indirect addressing modes. 
   
• CX register: (Combination of CL and CH Registers)
  It holds the count for instructions like a loop, rotates, shifts and string operations. 
   
• DX register: (Combination of DL and DH Registers)
  It is used with AX to hold 32-bit values during multiplication and division. 
   

Arithmetic Logic Unit (16-bit): Performs 8 and 16-bit arithmetic and logic operations. 

Special purpose registers (16-bit): Special purpose registers are called Offset registers also. Which points to specific memory locations under each segment.

We can understand the concept of segments as Textbook pages. Suppose there are 10 chapters in one textbook and each chapter takes exactly 100 pages. So the book will contain 1000 pages. Now suppose we want to access page number 575 from the book then 500 will be the segment base address which can be anything in the context of microprocessors like Code, Data, Stack, and Extra Segment. So 500 will be segment registers that are present in Bus Interface Unit (BIU). And 500 + 75 is called an offset register through which we can reach on specific page number under a specific segment.

Hence 500 is the segment base address and 75 is an offset address or (Instruction Pointer, Stack Pointer, Base Pointer, Source Index, Destination Index) any of the above according to their segment implementation.

• Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during instructions like PUSH, POP, CALL, RET etc.
• Base Pointer: BP can hold the offset addresses of any location in the stack segment. It is used to access random locations of the stack.
• Source Index: It holds offset address in Data Segment during string operations.
• Destination Index: It holds offset address in Extra Segment during string operations.

Instruction Register and Instruction Decoder: 

The EU fetches an opcode from the queue into the instruction register. The instruction decoder decodes it and sends the information to the control circuit for execution. 

Flag/Status register (16 bits): It has 9 flags that help change or recognize the state of the microprocessor. 

6 Status flags: 

1. Carry flag(CF)
2. Parity flag(PF)
3. Auxiliary carry flag(AF)
4. Zero flag(Z)
5. Sign flag(S)
6. Overflow flag (O)

Status flags are updated after every arithmetic and logic operation. 

3 Control flags: 

1. Trap flag(TF)
2. Interrupt flag(IF)
3. Direction flag(DF)

These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI, etc. The Control flags are used to control certain operations. 

 

4.Decode unit:

The Decode Unit in the 8086 microprocessor is a component that decodes the instructions that have been fetched from memory. The decode unit takes the machine code instructions and translates them into micro-operations that can be executed by the microprocessor’s execution unit.

The Decode Unit works in parallel with the Prefetch Unit, which fetches instructions from memory and stores them in a queue. The Decode Unit reads the instructions from the queue and translates them into micro-operations that can be executed by the microprocessor.

The Decode Unit is an important component of the 8086 microprocessor, as it allows the microprocessor to execute instructions efficiently and accurately. The decode unit ensures that the microprocessor can execute complex instructions, such as jump instructions and loop instructions, by translating them into a series of simple micro-operations.

The Decode Unit is responsible for decoding instructions, performing register-to-register operations, and performing memory-to-register operations. It also decodes conditional jumps, calls, and returns, and performs data transfers between memory and registers.

The Decode Unit helps to improve the performance of the 8086 microprocessor by allowing it to execute instructions quickly and accurately. This improved performance helps to ensure that the 8086 remains competitive in its performance and capabilities, even as technology continues to advance.

5.control unit :

The Control Unit in the 8086 microprocessor is a component that manages the overall operation of the microprocessor. The control unit is responsible for controlling the flow of instructions through the microprocessor and coordinating the activities of the other components, including the Decode Unit, Execution Unit, and Prefetch Unit.

The Control Unit acts as the central coordinator for the microprocessor, directing the flow of data and instructions and ensuring that the microprocessor operates correctly. It also monitors the state of the microprocessor, ensuring that the correct sequence of operations is followed.

The Control Unit is responsible for fetching instructions from memory, decoding them, executing them, and updating the microprocessor’s state. It also handles interrupt requests and performs system management tasks, such as power management and error handling.

The Control Unit is an essential component of the 8086 microprocessor, as it allows the microprocessor to operate efficiently and accurately. The control unit ensures that the microprocessor can execute complex instructions, such as jump instructions and loop instructions, by coordinating the activities of the other components.

The Control Unit helps to improve the performance of the 8086 microprocessor by managing the flow of instructions and data through the microprocessor, ensuring that the microprocessor operates correctly and efficiently. This improved performance helps to ensure that the 8086 remains competitive in its performance and capabilities, even as technology continues to advance.

The 8086 microprocessor uses three different buses to transfer data and instructions between the microprocessor and other components in a computer system. These buses are:

1.Address Bus: The address bus is used to send the memory address of the instruction or data being read or written. The address bus is 16 bits wide, allowing the 8086 to address up to 64 kilobytes of memory.

2.Data Bus: The data bus is used to transfer data between the microprocessor and memory. The data bus is 16 bits wide, allowing the 8086 to transfer 16-bit data words at a time.

3.Control Bus: The control bus is used to transfer control signals between the microprocessor and other components in the computer system. The control bus is used to send signals such as read, write, and interrupt requests, and to transfer status information between the microprocessor and other components.

The buses in the 8086 microprocessor play a crucial role in allowing the microprocessor to access and transfer data from memory, as well as to interact with other components in the computer system. The 8086’s ability to use these buses efficiently and effectively helps to ensure that it remains competitive in its performance and capabilities, even as technology continues to advance.

Execution of whole 8086 Architecture:

1. All instructions are stored in memory hence to fetch any instruction first task is to obtain the Physical address of the instruction is to be fetched. Hence this task is done by Bus Interface Unit (BIU) and by Segment Registers. Suppose the Code segment has a Segment address and the Instruction pointer has some offset address then the physical address calculator circuit calculates the physical address in which our instruction is to be fetched.
2. After the address calculation instruction is fetched from memory and it passes through C-Bus (Data bus) as shown in the figure, and according to the size of the instruction, the instruction pre-fetch queue fills up. For example MOV AX, BX is 1 Byte instruction so it will take only the 1st block of the queue, and MOV BX,4050H  is 3 Byte instruction so it will take 3 blocks of the pre-fetch queue.
3. When our instruction is ready for execution, according to the FIFO property of the queue instruction comes into the control system or control circuit which resides in the Execution unit. Here instruction decoding takes place. The decoding control system generates an opcode that tells the microprocessor unit which operation is to be performed. So the control system sends signals all over the microprocessor about what to perform and what to extract from General and Special  Purpose Registers.
4. Hence after decoding microprocessor fetches data from GPR and according to instructions like ADD, SUB, MUL, and DIV data residing in GPRs are fetched and put as ALU’s input. and after that addition, multiplication, division, or subtraction whichever calculation is to be carried out. 
5. According to arithmetic, flag register values change dynamically.
6. While Instruction was decoding and executing from step-3 of our algorithm, the Bus interface Unit doesn’t remain idle. it continuously fetches an instruction from memory and put it in a pre-fetch queue and gets ready for execution in a FIFO manner whenever the time arrives.
7. So in this way, unlike the 8085 microprocessor, here the fetch, decode, and execution process happens in parallel and not sequentially. This is called pipelining, and because of the instruction pre-fetch queue, all fetching, decoding, and execution process happen side-by-side. Hence there is partitioning in 8086 architecture like Bus Interface Unit and Execution Unit to support Pipelining phenomena. 
   

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8. 
   

Introduction to 8086 Microprocessor Architecture

The 8086 microprocessor, developed by Intel in 1978, was a groundbreaking 16-bit processor that laid the foundation for modern computing. It introduced significant advancements over its predecessors, such as improved instruction sets, pipelining, and memory segmentation. The 8086 architecture became the basis for the x86 architecture, which still dominates the computing industry today.

• The 8086 microprocessor works as a complex instruction set computer (CISC) because its instruction set includes different commands that can do more than one thing with just one instruction. 
• With its 20-bit address bus, the 8086 processor obtains memory access up to 1 MB, while its 16-bit data bus enables data movement between the processor and memory and I/O resources.
• Memory segments in the 8086 microprocessor require both a segment register and an offset for address retrieval.
•  Each segment begins at its designated address through the segment register before moving to a specific byte by utilizing the offset as its reference point. 
• The 8086 microprocessor can handle elevated memory quantities using its 16-bit data bus structure.

An 8086 microprocessor contains two primary execution units : the execution unit (EU) together with the bus interface unit (BIU). Until the Execution Unit (EU) does the actual instruction execution, the Bus Interface Unit (BIU) is in charge of getting memory instructions and decoding them. The BIU controls data movement that occurs between the microprocessor and memory and input-output devices.

There are a lot of register functions in the 8086 microprocessor. These include 

1. general-purpose storage areas, 
2. segment storage, and 
3. specific storage units. 

All registers present in the 8086 operate in two distinct ways: General-purpose registers can store data and run mathematical functions. Segment registers, on the other hand, let you directly access memory segments. Special registers consist of two primary components known as the flags register and instruction pointer, which function as status information memory and next instruction address, respectively.

Architecture of 8086 or Functional Block diagram of 8086  

 8086 has two blocks Bus Interface Unit (BIU) and Execution Unit (EU). 

 The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. 

 EU executes instructions from the instruction system byte queue.  

 Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. 

 BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. 

 EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.   

Advantages of Architecture of 8086:

The architecture of the 8086 microprocessor provides several advantages, including:

1. Wide range of instructions: The 8086 microprocessor supports a wide range of instructions, allowing programmers to write complex programs that can perform many different operations.
2. Segmented memory architecture: The segmented memory architecture allows the 8086 microprocessor to address large amounts of memory, up to 1 MB, while still using a 16-bit data bus.
3. Powerful instruction set: The instruction set of the 8086 microprocessor includes many powerful instructions that can perform multiple operations in a single instruction, reducing the number of instructions needed to perform a given task.
4. Multiple execution units: The 8086 microprocessor has two main execution units, the execution unit and the bus interface unit, which work together to efficiently execute instructions and manage data transfer.
5. Rich set of registers: The 8086 microprocessor has a rich set of registers, including general-purpose registers, segment registers, and special registers, allowing programmers to efficiently manipulate data and control program flow.
6. Backward compatibility: The architecture of the 8086 microprocessor is backward compatible with earlier 8-bit microprocessors, allowing programs written for these earlier microprocessors to be easily ported to the 8086 microprocessor.

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What’s difference between Microcontroller (µC) and Microprocessor (µP)

A microcontroller (µC) contains not only a processing unit but a small amount of memory (ROM, RAM, etc.), a few IO ports for peripherals, a timer, etc. We can think of a microcontroller as a mini-computer. But a microprocessor (µP) contains only a processing unit which is quite powerful in terms of computing. To make use of a microprocessor (µP), one needs extra hardware chips such as memory (RAM), peripheral boards, system bus, etc. but nowadays modern SoCs integrate multiple components (CPU, memory, peripherals) on a single chip, and are considered part of the microprocessor family due to their central processing capabilities. 

Based on the application’s requirements we can determine whether microcontroller or microprocessor is best. Microcontrollers are the solution for fundamental control tasks that are cost-effective. Microprocessors are an improved choice for advanced, powerful computing. For particular control-oriented applications, microcontrollers offer highly integrated, cheap, and power-efficient alternates. Microprocessors are more adaptable and powerful computational units that are well-suited for harder and more involved activities that call for significant processing power and additional components.

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Memory Interfacing and IO Interfacing with 8085

 

Interface is the path for communication between two components. Interfacing is of two types, memory interfacing and I/O interfacing.

Memory Interfacing

When we are executing any instruction, we need the microprocessor to access the memory for reading instruction codes and the data stored in the memory. For this, both the memory and the microprocessor requires some signals to read from and write to registers.

The interfacing process includes some key factors to match with the memory requirements and microprocessor signals. The interfacing circuit therefore should be designed in such a way that it matches the memory signal requirements with the signals of the microprocessor.

IO Interfacing

There are various communication devices like the keyboard, mouse, printer, etc. So, we need to interface the keyboard and other devices with the microprocessor by using latches and buffers. This type of interfacing is known as I/O interfacing.

Block Diagram of Memory and I/O Interfacing

8085 Interfacing Pins

Following is the list of 8085 pins used for interfacing with other devices −

• A₁₅ - A₈ (Higher Address Bus)
• AD₇ - AD₀(Lower Address/Data Bus)
• ALE
• RD
• WR
• READY

Ways of Communication − Microprocessor with the Outside World?

There are two ways of communication in which the microprocessor can connect with the outside world.

• Serial Communication Interface
• Parallel Communication interface

Serial Communication Interface − In this type of communication, the interface gets a single byte of data from the microprocessor and sends it bit by bit to the other system serially and vice-a-versa.

Parallel Communication Interface − In this type of communication, the interface gets a byte of data from the microprocessor and sends it bit by bit to the other systems in simultaneous (or) parallel fashion and vice-a-versa.

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Block Diagram of a Microprocessor

 

Block Diagram of a Microprocessor

A Microprocessor takes a bunch of instructions in machine language and executes them, telling the processor what it has to do. The microprocessor performs three basic things while executing the instruction: 

• It performs some basic operations like addition, subtraction, multiplication, division, and some logical operations using its Arithmetic and Logical Unit (ALU). New Microprocessors also perform operations on floating-point numbers. 
• Data in microprocessors can move from one location to another. 
• It has a Program Counter (PC) register that stores the address of the next instruction based on the value of the PC, Microprocessor jumps from one location to another and makes decisions. 

Clock Speed of different Microprocessor: 

• 16-bit Microprocessor

8086: 4.7MHz, 8MHz, 10MHz

8088: more than 5MHz

80186/80188: 6MHz

80286: 8MHz 

• 32-bit Microprocessor

INTEL 80386: 16MHz to 33MHz

INTEL 80486: 16MHz to 100MHz

PENTIUM: 66MHz 

• 64-bit Microprocessor

INTEL CORE-2: 1.2GHz to 3GHz

INTEL i7: 66GHz to 3.33GHz

INTEL i5: 2.4GHz to 3.6GHz

INTEL i3: 2.93GHz to 3.33GHz 

We do not have any 128-bit Microprocessor at work at present one of the reasons for this is that we are a long way from exhausting the 64-bit address space itself, we use it at a constant rate of roughly 2 bits every 3 years. At present we have only used 48 bits of 64 bits so why require 128-bit address space. Also, 128-bit Microprocessor would be much slower than the 64 bit Microprocessor. 

Types of Processor

Complex Instruction Set Computer (CISC)

CISC or Complex Instruction Set Computer is a computer architecture where instructions are such that a single instruction can execute multiple low-level operations like loading from memory, storing into memory, or an arithmetic operation, etc. It has multiple addressing nodes within a single instruction. CISC makes use of very few registers. 

Example of CISC are

• Intel 386
• Intel 486
• Pentium
• Pentium Pro
• Pentium II
• Pentium III
• Motorola 68000
• Motorola 68020
• Motorola 68040 etc.

Reduced Instruction Set Computer (RISC)

RISC or Reduced Instruction Set Computer is a computer architecture where instruction is simple and designed to get executed quickly. Instructions get completed in one clock cycle this is because of the optimization of instructions and pipelining (a technique that allows for simultaneous execution of parts, or stages, of instructions more efficiently process instructions). RISC makes use of multiple registers to avoid large interactions with memory. It has few addressing nodes. 

Example of RISC are

• IBM RS6000
• MC88100
• DEC Alpha 21064
• DEC Alpha 21164
• DEC Alpha 21264

Explicitly Parallel Instruction Computing (EPIC)

EPIC or Explicitly Parallel Instruction Computing permits computers to execute instructions parallel using compilers. It allows complex instructions execution without using higher clock frequencies. EPIC encodes its instruction into 128-bit bundles. each bundle contains three instructions which are encoded in 41 bits each and a 5-bit template field(contains information about types of instructions in a bundle and which instructions can be executed in parallel). 

Example of EPIC is

• IA-64 (Intel Architecture-64)

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